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Adder circuit model with SystemC events

Adder circuit model with SystemC signals

Adder circuit model with handshaking ready/valid signals

Adder circuit model with SystemC FIFO

for lab1 on 3/14

https://github.com/gem5bootcamp/2024.git

Develop ideal SystemC code of Stencil circuit

picorv32_fault_injection_system run on Alveo_U50_FPGA

Sobel filter module with FIFO interfaces.