update adalen testbench

scripts/adaline_demo/testbench.v

-`timescale 1 ns / 1 ps
+`timescale 1 fs / 1 fs
 `undef VERBOSE_MEM
-`undef WRITE_VCD
+//`undef WRITE_VCD
+`define WRITE_VCD
 `undef MEM8BIT
 
 module testbench;
@@ -22,6 +23,9 @@ module testbench;
 	wire [31:0] mem_wdata;
 	wire [3:0] mem_wstrb;
 	reg  [31:0] mem_rdata;
+	reg  [63:0] cycle = 0;
+	reg  [7:0] result [1:4096];
+    integer idx = 1;
 
 	picorv32 #(
 		.COMPRESSED_ISA(1)
@@ -48,6 +52,7 @@ module testbench;
 `endif
 
 	always @(posedge clk) begin
+        cycle <= cycle + 1;
 		mem_ready <= 0;
 		if (mem_valid && !mem_ready) begin
 			mem_ready <= 1;
@@ -75,7 +80,9 @@ module testbench;
 `endif
 				end
 				mem_addr == 32'h 1000_0000: begin
-					$write("%c", mem_wdata[7:0]);
+                    result[idx] <= mem_wdata[7:0];
+                    idx = idx + 1; 
+					//$write("%c", mem_wdata[7:0]);
 				end
 			endcase
 		end
@@ -99,8 +106,30 @@ module testbench;
 
 `ifdef WRITE_VCD
 	initial begin
-		$dumpfile("testbench.vcd");
-		$dumpvars(0, testbench);
+		$dumpfile("decoder.vcd");
+        //$dumpvars(0, testbench);
+		
+        $dumpvars(0, 
+            cycle,
+            uut.dbg_ascii_state,
+            uut.dbg_ascii_instr,
+            uut.cpu_state,
+            uut.count_instr,
+            uut.decoder_trigger_q,
+            uut.instr_lui,
+            uut.instr_auipc,
+            uut.instr_jalr,
+            uut.is_lb_lh_lw_lbu_lhu,
+            uut.is_alu_reg_imm,
+            uut.is_beq_bne_blt_bge_bltu_bgeu,
+            uut.decoder_trigger,
+            uut.decoder_pseudo_trigger,
+            uut.mem_do_rinst,
+            uut.mem_done,
+            uut.mem_xfer,
+            uut.mem_rdata_q
+        );
+        
 	end
 `endif
 
@@ -108,6 +137,13 @@ module testbench;
 		if (resetn && trap) begin
 			repeat (10) @(posedge clk);
 			$display("TRAP");
+            /*
+            idx = 1;
+            while(idx <= 4096)begin
+                $write("%c", result[idx]);
+                idx = idx + 1;
+            end
+            */
 			$finish;
 		end
 	end